RISC Architecture Process Pipelining Techniques


RISC refers to a designs philosophy that is targeted at reducing how complex instruction set with the aim of reducing cycle time, space, power consumption and cost required during implementation of a design. The existing system design uses the Arithmetic and Logic unit and it has various challenges the needs to be addresses. For instance, ALU perform basic arithmetic such as SUB, ADD, DIV, MUL and other logical operations such as AND, NOT, NOR, NAND, XNOR and XOR operations that consume a lot of power [1]. As such, there is a need to correct the challenges by introducing 16-bit processor. 16-bit processor is a low-power processor and it is consisted of a blocks of ALU, Barrel Shifter and Universal Shift.


In basic term, ALU can be described as a combinational electronic circuit that has the ability to perform bitwise logical operations and arithmetic and produces outcome of the performed operations. ALU has the capacity to exchange information with status register. However, ALU operations consume a lot of power and space. As such, RISC processor is the best alternative to be considered in overcoming the shortcomings of ALU processor [2].


Features of ALU

History of ALU

RISC Processor

The RISC processor CPU has the capabilities of executing small set of instructions using very short time. A ROSC architecture is characterized by with less instructions and it involves assessing data from memory rather than other loads.

RSIC Architecture

The main feature of RISC architecture is minimum amount of time that is required for execution. It also uses highly optimized and small set of instructions that mainly operates in register-to-register operations.

The less time required for execution purposes is supported by the fact that the system uses a small number of instructions.

Proposed 16-Bit RISC Processor

The 16-bit RISC processor is comprised of barrel shifter, ALU, purpose register, universal shift register, general purpose register, control unit, and an accumulator. However, it is important to note that the control unit also has two important registers[3]. These include instruction decoder and instruction register.

Simulation Results

The outcome of the simulation process reveals the unassigned decimal, which is a representation of 16-bit RISC processor. The operations are performed based on the values of rst and clk. As such, the outputs of portrd and portwr are representations of memory operations. The binary representation from the simulation is based a processor of 16-bit[4]. This is also based on the rst and clk operations. Even here, the portrd and portwr are representations of memory operations.

The RTL schematic of the intended processor development has different inputs and outputs.

Even more, the system technology that is being used has huge number of LUTs.

The 16-bit RISC processor consumes very less power when compared to the other existing processor.

Discussion of Results

The 26-bit RISC processor uses very less power because of its computing capabilities. The proposed processor that is based on RISC consumes power that is less than 1W implying that it can process more operations and for a longer period. Low power consumption is a critical factor that improves the efficiency of the processor. Furthermore, it supports faster execution of processes. This is the reason behind a higher speed of operation when compared to the existing processor.


[1] Shehan, B., Jahr, R., Uhrig, S., & Ungerer, T. (2010, September). Reconfigurable grid ALU processor: Optimization and design space exploration. In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (pp. 71-79). IEEE.

[2] Trivedi, P., & Tripathi, R. P. (2015, May). Design & analysis of 16 bit RISC processor using low power pipelining. In International Conference on Computing, Communication & Automation (pp. 1294-1297). IEEE.

[3] Uhrig, S., Shehan, B., Jahr, R., & Ungerer, T. (2009, November). A two-dimensional superscalar processor architecture. In 2009 Computation World: Future Computing, Service Computation, Cognitive, Adaptive, Content, Patterns (pp. 608-611). IEEE.

[4] Yi, K., & Ding, Y. H. (2009, April). 32 Bit multiplication and division ALU design based on RISC structure. In 2009 International Joint Conference on Artificial Intelligence (pp. 761-764). IEEE.

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